A wide variety of implantable medical devices (IMDs) that employ electronic circuitry for providing various therapies such as electrical stimulation of body tissue, monitoring a physiologic condition, and/or providing a substance are known in the art. For example, cardiac pacemakers and implantable cardioverter-defibrillators (ICDs) have been developed for maintaining a desired heart rate during episodes of bradycardia or for applying cardioversion or defibrillation therapies to the heart upon detection of serious arrhythmias. Other devices deliver drugs to the brain, muscle and organ tissues, and/or nerves for treatment of a variety of conditions.
Over the past 20 years, the IMDs have evolved from relatively bulky, crude, and short-lived devices to complex, long-lived, and miniaturized IMDs that are steadily being miniaturized with their functionality continuously increasing. For example, numerous improvements have been made in cardioversion/defibrillation leads and electrodes that have enabled the cardioversion/defibrillation energy to be precisely delivered about selected upper and lower heart chambers and thereby dramatically reducing the delivered shock energy required to cardiovert or defibrillate the heart chamber. Moreover, the high voltage output circuitry has been improved in many respects to provide monophasic, biphasic, or multi-phase cardioversion/defibrillation shock or pulse waveforms that are efficacious, sometimes with particular combinations of cardioversion/defibrillation electrodes, in lowering the required shock energy to cardiovert or defibrillate the heart.
The miniaturization of IMDs is driving size and cost reduction of all IMD components including the electronic circuitry components, where it is desirable to reduce the size so that the overall circuitry can be more compact. As the dimensions of the IMDs decreases, the electronic circuits of the IMD circuitry are preferred to decrease power consumption in order to maintain or increase longevity. Noticeably, the miniaturization of IMDs has taken advantage of the developments in CMOS (Complementary Metal-Oxide Semiconductor) technology, which has led to the development of single-chip processors (e.g., microprocessors) with ever increasing clocking speeds that can be clocked separately from other circuitry components of the IMD for efficient data processing and power management.
When there is a difference between the speed at which a signal input to a receiving circuit is transmitted and a speed at which the receiving circuit is enabled, a so-called race condition can occur. The race condition is manifested in many ways as has been discussed in the art. For example, depending on the relationship between the frequencies under which different circuits in an IMD are operated, the receiving circuit may attempt to sample the transmitted data during periods when the data is in a quasi-stable state. Such a state may exist during the active clock edge of the clock signals of the transmitting circuit. Attempts by the receiving circuit to read the data during such periods that are aligned with the active clock edges of the clock signal clocking the transmitting circuit may impact the integrity of data transferred between such circuits. As such, many solutions have focused on avoiding reading the data during such times as that where race conditions would arise to ensure that the data will be stable when sampled.
In conventional circuits, one such approach to transferring the data between circuits clocked at different speeds has been to skew the clocks. An example of this approach is discussed in U.S. Pat. No. 7,765,425 issued to Searles et al. In high frequency environments, the uncertainty in the timing relationship between the two clocks may approach the clock period of the faster clock signal and when this occurs, skewing the clocks is not sufficient to ensure accurate data transfer.
Another approach to eliminate the data and processing errors associated with the so-called race condition has been to turn off the higher frequency clock or to inhibit the higher frequency signal during the data transfer operations. By doing so, the circuits of the IMD are operated only under the lower frequency signal generated by the lower frequency clock during the data transfer operations. An example of such an approach is discussed in commonly assigned U.S. Pat. No. 7,085,952 issued to Huelskamp and which is incorporated herein by reference in its entirety. The '952 patent discusses considerations that may be needed as a result of the transitions between the lower and higher clock frequency signals. Another example is discussed in U.S. Pat. No. 5,022,395 issued to Russie.
In yet another approach, the solution to race conditions is to synchronize the edges of the higher frequency clock with the edges of the lower frequency clock. Such a solution utilizes a clock synchronizer that may utilize a phase-locked loop (PLL) circuit to synchronize the clock edges. An example of this approach is discussed in U.S. Pat. No. 7,436,917 to Adkisson et al.
However, the conventional solutions result in increased overall circuitry components to achieve the desired functionality and increase the complexity of the IMD. Additionally, the solutions have resulted in increased latency as well as increased current drain.
The potential for realizing a race condition becomes even more pronounced with attempts at achieving higher and higher clocking speeds. The race conditions can cause the wrong data value to be read when the data is sampled which can cause inaccurate operation (e.g., glitches or spurous transitions, etc.) of the individual logic circuits and, therefore, of the overall circuitry in the IMD. In fact, such race conditions can adversely affect attempts to miniaturize and increase speeds in IMD circuitry.
It is desirable to continue to reduce size and power consumption while increasing and improving processing capabilities of such IMDs.